Digital to analog converter and method thereof

ABSTRACT

A digital to analog converter (DAC) has a plurality of transistor-resistor units connected in a string. Each of the transistor-resistor units of the DAC has a pair of transistors that are turned on/off by a pair of complementary control signals. Since the two transistors of each transistor-resistor unit are positioned symmetrically, an equivalent resistance would be determined precisely according to received digital codes, such that an output voltage of the DAC could be adjusted precisely based on the equivalent resistance.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of U.S. provisionalapplication Ser. No. 61/089,610, filed Aug. 18, 2008. The entirety ofthe above-mentioned patent application is hereby incorporated byreference herein and made a part of this specification.

BACKGROUND OF THE INVENTION

1. Field of Invention

The present invention is related to a digital to analog converter andmethod thereof, and more particularly, to a digital to analog converterand method thereof for outputting an output voltage at a desired voltagelevel precisely.

2. Description of Related Art

The digital to analog converter (DAC) is widely used in current digitalcircuits. Most microcontrollers have a DAC to perform the digital toanalog conversion operation. Please refer to FIG. 1, which is a circuitdiagram of a DAC 10 according to the prior art. The DAC 10 has anegative feedback regulator 12, a ladder circuit 16, and a referenceresistor R_(REF). The negative feedback regulator 12 has an operationalamplifier 14. The operational amplifier 14 has a positive input terminalcoupled to a reference voltage V_(REF), a negative input terminalcoupled to an end of the ladder circuit 16, and an output terminal foroutputting an output voltage V_(OUT). The ladder circuit 16 has aplurality of transistor-resistor units A₀-A_(N), where N is a positiveinteger. Each of the transistor-resistor units A₀-A_(N) has a transistorand a resistor coupled to the transistor in series. For example, thetransistor-resistor units A₀ has a transistor M₀ and a resistor R₀, andthe transistor M₀ is coupled to the resistor R₀ in series. Additionally,except the resistor R₀ of the transistor-resistor unit A₀, theresistance of the resistor R₁-R_(N) of each of the transistor-resistorunits A₁-A_(N) is 2^(i) times of that of the resistor R₀, where i is apositive integer. For example, R₁=2¹×R₀, R_(N)=2^(N)×R₀, etc. The gatesof the transistors M₀-M_(N) are biased by control voltages that areassociated with digital codes B ₀ to B _(N). For each of the controlvoltages, the control voltage is high while the associated digital codeis “1”, and the control voltage is low while the associated digital codeis “0”. For example, when the digital code B ₀ is “1”, the gate of thetransistor M₀ is biased by a high-level control voltage, such that thetransistor M₀ is turned on. When the digital code B ₀ is “0”, the gateof the transistor M₀ is biased by a low-level control voltage, such thatthe transistor M₀ is turned off. Therefore, each of the digital codes B₀to B_(N) is used to turn on/off a corresponding one of the transistorsM₀-M_(N), and the output voltage V_(OUT) could be determined as:

$\begin{matrix}{V_{OUT} = {{\begin{bmatrix}{{R_{ON} \times \left( {\overset{\_}{B_{0}} + \overset{\_}{B_{1}} + \ldots + \overset{\_}{B_{N}}} \right)} +} \\\left( {{R_{0}B_{0}} + {R_{1}B_{1}} + \ldots + {R_{N}B_{N}}} \right)\end{bmatrix} \times \frac{V_{REF}}{R_{REF}}} + V_{REF}}} & (1) \\{\mspace{59mu}{= {{\begin{bmatrix}{{R_{ON} \times \left( {\overset{\_}{B_{0}} + \overset{\_}{B_{1}} + \ldots + \overset{\_}{B_{N}}} \right)} +} \\\begin{pmatrix}{{{2\;}^{0}R_{0}B_{0}} +} \\{{{2\;}^{1}R_{0}B_{1}} + \ldots + {2^{N}R_{0}B_{N}}}\end{pmatrix}\end{bmatrix} \times \frac{V_{REF}}{R_{REF}}} + V_{REF}}}} & (2)\end{matrix}$where R_(ON) represents the resistance of each turned-on transistorM₀-M_(N), and each of B₀ to B_(N) represents an digital code that iscomplementary to a corresponding one of the digital codes B₀ to B_(N) .For example, B₀ and B₀ are complementary to each other; B₁ and B₁ arecomplementary to each other; and B_(N) and B_(N) are complementary toeach other.

Each of combinations of the digital codes B₀ to B_(N) is used todetermine a corresponding voltage level of the output voltage V_(OUT).In this case, it is assumed that a resistance R_(M) is described asfollows:R _(M) =R _(ON)×( B ₀ + B ₁ +. . . + B _(N) )  (3)

Therefore, the above equation (2) could be written as:

$\begin{matrix}{V_{OUT} = {{\left\lbrack {R_{M} + \begin{pmatrix}{{{2\;}^{0}R_{0}B_{0}} +} \\{{{2\;}^{1}R_{0}B_{1}} + \ldots + {2^{N}R_{0}B_{N}}}\end{pmatrix}} \right\rbrack \times \frac{V_{REF}}{R_{REF}}} + V_{REF}}} & (4) \\{\mspace{59mu}{= {{\begin{pmatrix}{{{2\;}^{0}R_{0}B_{0}} +} \\{{{2\;}^{1}R_{0}B_{1}} + \ldots + {2^{N}R_{0}B_{N}}}\end{pmatrix} \times \frac{V_{REF}}{R_{REF}}} + {\left( {1 + \frac{R_{M}}{R_{REF}}} \right)V_{REF}}}}} & (5)\end{matrix}$

Generally, in order to output the output voltage V_(OUT) at a desiredlevel more precisely, it is desired that the value of

$\left( {\left( {1 + \frac{R_{M}}{R_{REF}}} \right) \times V_{REF}} \right)$is a constant. However, according to the equation (3), the resistanceR_(M) varies with the digital codes B₀ to B_(N) , such that it isdifficult to precisely output the output voltage V_(OUT) at a desiredlevel.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a digitalto analog converter for outputting a desired output voltage precisely.The digital to analog converter comprises an operational amplifier and aladder circuit. The operational amplifier has an output terminal foroutputting an output voltage. The ladder circuit is coupled to theoutput terminal and has a plurality of transistor-resistor unitsconnected in a string. Each of the transistor-resistor units has aresistor, a first transistor coupled to the resistor in series, and asecond transistor coupled to the resistor and the first transistor inparallel.

A further object of the present invention is to provide a digital toanalog converting method for converting a plurality of digital codesinto an output voltage. The method comprises inputting the plurality ofdigital codes; generating a pair of complementary control signals foreach of the digital codes; applying the pairs of complementary controlsignals to a series of pairs of transistors to determine an equivalentresistance; and outputting the output voltage based on the equivalentresistance.

According to an exemplary embodiment of the present invention, themethod further comprises providing a reference voltage and comparing thereference voltage with a terminal voltage of the series of pairs oftransistors to refresh the output voltage.

According to an exemplary embodiment of the present invention, the firsttransistor is turned on while the second transistor is turned off, andthe first transistor is turned off while the second transistor is turnedon.

According to an exemplary embodiment of the present invention, aturned-on resistance of the first transistor is equal to a turned-onresistance of the second transistor.

According to an exemplary embodiment of the present invention, theoperational amplifier further has a first input terminal coupled to areference voltage and a second input terminal coupled to one end of theladder circuit.

According to an exemplary embodiment of the present invention, thedigital to analog converter further comprises a reference resistorcoupled between the second input terminal and a ground terminal.

According to an exemplary embodiment of the present invention, the firsttransistor and the second transistor are n-channelmetal-oxide-semiconductor field-effect transistors (NMOSFETs). Each ofthe NMOSFETs has a body and a source coupled to the body.

According to an exemplary embodiment of the present invention, the firsttransistor and the second transistor are p-channelmetal-oxide-semiconductor field-effect transistors (PMOSFETs). Each ofthe PMOSFETs has a body and a source coupled to the body.

In order to make the aforementioned and other objects, features andadvantages of the present invention comprehensible, several preferredembodiments accompanied with figures are described in detail below.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary, and are intended toprovide further explanation of the invention as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are included to provide a furtherunderstanding of the invention, and are incorporated in and constitute apart of this specification. The drawings illustrate embodiments of theinvention and, together with the description, serve to explain theprinciples of the invention.

FIG. 1 is a circuit diagram of a DAC according to the prior art.

FIG. 2 is a circuit diagram of a DAC according to an embodiment of thepresent invention.

FIG. 3 is a circuit diagram of a DAC according to another embodiment ofthe present invention.

FIG. 4 is a circuit diagram of a DAC according to another embodiment ofthe present invention.

DESCRIPTION OF EMBODIMENTS

Please refer to FIG. 2, which is a circuit diagram of a DAC 20 accordingto an embodiment of the present invention. The DAC 20 has the negativefeedback regulator 12, the reference resistor R_(REF), and a laddercircuit 22. The positive input terminal of the operational amplifier 14of the negative feedback regulator 12 is coupled to the referencevoltage V_(REF), the negative input terminal of the operationalamplifier 14 is coupled to an end Y of the ladder circuit 16, and theoutput terminal of the operational amplifier 14 outputs the outputvoltage V_(OUT). The reference resistor R_(REF) is coupled between thenegative input terminal of the operational amplifier 14 and a groundterminal. An end X of the ladder circuit 22 is coupled to the outputterminal of the operational amplifier 14, and the other end Y of theladder circuit 22 is coupled to the reference resistor R_(REF) and thenegative input terminal of the operational amplifier 14. A terminalvoltage V_(b) of the ladder circuit 22 at the end Y is inputted to thenegative input terminal of the operational amplifier 14, such that theoperational amplifier 14 would compare the reference voltage V_(REF)with the terminal voltage V_(b) to refresh the output voltage V_(OUT).The ladder circuit 22 has a plurality of transistor-resistor unitsI₀-I_(N) connected in a string, where N is a positive integer. Each ofthe transistor-resistor units I₀-I_(N) has a resistor, a firsttransistor coupled to the resistor in series, and a second transistorcoupled to the resistor and the first transistor in parallel. Forexample, the transistor-resistor units I₀ has resistor R₀, a firsttransistor Q₀ coupled to the resistor R₀ in series, and a secondtransistor M₀ coupled to the resistor R₀ and the first transistor Q₀ inparallel. Additionally, except the resistor R₀ of thetransistor-resistor unit I₀, the resistance of the resistor R₁-R_(N) ofeach of the transistor-resistor units A₁-A_(N) is 2^(i) times of that ofthe resistor R₀, where i is a positive integer. For example, R₁=2¹×R₀,R_(N)=2^(N)×R₀, etc. The gates of the first transistors Q₀-Q_(N) arebiased by control voltages that are associated with digital codesB₀-B_(N), and the gates of the second transistors M₀-M_(N) are biased bycontrol voltages that are associated with digital codes B₀ to B_(N) .Each of the digital codes B₀ to B_(N) represents a digital code that iscomplementary to a corresponding one of the digital codes B₀ to B_(N).For example, B₀ and B₀ are complementary to each other; B₁ and B₁ arecomplementary to each other; and B_(N) and B_(N) are complementary toeach other. For each of the control voltages, the control voltage ishigh while the associated digital code is “1”, and the control voltageis low while the associated digital code is “0”. For example, when thedigital code B₀ is “1”, the gate of the first transistor Q₀ is biased bya high-level control voltage, such that the first transistor Q₀ isturned on. Meanwhile, the digital code B₀ is “0”, and the gate thesecond transistor M₀ is biased by a low-level control voltage, such thatthe second transistor M₀ is turned off. On the other hand, when thedigital code B₀ is “0”, the gate of the first transistor Q₀ is biased bya low-level control voltage, such that the first transistor Q₀ is turnedoff. Meanwhile, the digital code B₀ is “1”, and the gate the secondtransistor M₀ is biased by a high-level control voltage, such that thesecond transistor M₀ is turned on. Briefly, for each of the digitalcodes B₀-B_(N), a pair of complementary control signals are generatedand applied to a pair of the first transistor and the second transistorof a corresponding one of the transistor-resistor units A₁-A_(N), suchthat an equivalent resistance R_(EQ) of the ladder circuit 22 could bedetermined as:

$\begin{matrix}{R_{EQ} = \left\lbrack {{\left( {R_{0} + R_{ON}} \right) \times B_{0}} + {\left( {R_{1} + R_{ON}} \right) \times B_{1}} + \ldots + {\left( {R_{N} + R_{ON}} \right) \times B_{N}}} \right\rbrack} & (6)\end{matrix} + {R_{ON} \times \left( {\overset{\_}{B_{0}} + \overset{\_}{B_{1}} + \ldots + \overset{\_}{B_{N}}} \right)}$where R_(ON) represents the resistance of each turned-on transistoramong the first transistors Q₀-Q_(N) and the second transistorsM₀-M_(N). In other words, each of the first transistors Q₀-Q_(N) and thesecond transistors M₀-M_(N) has the same turned-on resistance.

The output voltage V_(OUT) could be determined based on the equivalentresistance R_(EQ) as follows:

$\begin{matrix}{V_{OUT} = {{R_{EQ} \times \frac{V_{REF}}{R_{REF}}} + V_{REF}}} & (7)\end{matrix}$

Additionally, the equation (7) could be rewritten according to theequation (6), such that the output voltage V_(OUT) could be calculatedas follow:

$\begin{matrix}{V_{OUT} = {{\begin{bmatrix}{{\left( {R_{0} + R_{ON}} \right) \times B_{0}} + {\left( {R_{1} + R_{ON}} \right) \times}} \\{B_{1} + \ldots + {\left( {R_{N} + R_{ON}} \right) \times B_{N}} +} \\{R_{ON} \times \left( {\overset{\_}{B_{0}} + \overset{\_}{B_{1}} + \ldots + \overset{\_}{B_{N}}} \right)}\end{bmatrix} \times \frac{V_{REF}}{R_{REF}}} + V_{REF}}} & (8) \\{\mspace{56mu}{= {{\left\{ {R_{ON} \times \begin{matrix}{\begin{bmatrix}{\left( {\overset{\_}{B_{0}} + \overset{\_}{B_{1}} + \ldots + \overset{\_}{B_{N}}} \right) +} \\\left( {B_{0} + B_{1} + \ldots + B_{N}} \right)\end{bmatrix} +} \\\left( {{R_{0}B_{0}} + {R_{1}B_{1}} + \ldots + {R_{N}B_{N}}} \right)\end{matrix}} \right\} \times \frac{V_{REF}}{R_{REF}}} + V_{REF}}}\mspace{20mu}} & (9) \\{\mspace{56mu}{= {{\begin{Bmatrix}{{R_{ON} \times N} +} \\\begin{pmatrix}{{2^{0}R_{0}B_{0}} +} \\{{2^{1}R_{0}B_{1}} + \ldots + {2^{N}R_{0}B_{N}}}\end{pmatrix}\end{Bmatrix} \times \frac{V_{REF}}{R_{REF}}} + V_{REF}}}} & (10) \\{\mspace{56mu}{= {{\begin{pmatrix}{{2^{0}R_{0}B_{0}} +} \\{{2^{1}R_{0}B_{1}} + \ldots + {2^{N}R_{0}B_{N}}}\end{pmatrix} \times \frac{V_{REF}}{R_{REF}}} + {\left( {1 + \frac{R_{ON} \times N}{R_{REF}}} \right) \times V_{REF}}}}} & (11)\end{matrix}$

In the equation (11), the term

$\left( {\left( {1 + \frac{R_{ON} \times N}{R_{REF}}} \right) \times V_{REF}} \right)$is a constant. Therefore, the voltage level of the output voltageV_(OUT) could be precisely adjusted according to the digital codesB₀-B_(N).

Please refer to FIG. 3, which is a circuit diagram of a DAC 30 accordingto another embodiment of the present invention. The DAC 30 is similar tothe DAC 20 shown in FIG. 2. The major difference between the DAC 30 andthe DAC 20 is that the first transistors Q₀-Q_(N) and the secondtransistors M₀-M_(N) of the DAC 20 are replaced with the n-channelmetal-oxide-semiconductor field-effect transistors (NMOSFETs) N₀-N_(N)and NM₀-NM_(N). Each of the NMOSFETs N₀-N_(N) and NM₀-NM_(N) has a bodyand a source coupled to the body. The DAC 30 also has the negativefeedback regulator 12, the reference resistor R_(REF), and a laddercircuit 32. The ladder circuit 32 has a plurality of transistor-resistorunits G₀-G_(N) connected in a string. In the embodiment, the resistanceof each turned-on transistor R_(ON) could be calculated as follows:

$\begin{matrix}{R_{ON} = {\mu \times C_{OX} \times \frac{W}{L}\left( {V_{GS} - V_{T}} \right)}} & (12)\end{matrix}$where μ represents the mobility of the turned-on transistor;

C_(OX) represents the gate oxide capacitance per unit area;

W represents the gate width of the turned-on transistor;

L represents the gate length of the turned-on transistor;

V_(GS) represents the gate-source voltage of the turned-on transistor;and

V_(T) represents the threshold voltage of the turned-on transistor.

The threshold voltage V_(T) could be determined as follows:V _(T) =V _(TO)+γ(√{square root over (V _(SB)+2φ)}−√{square root over(2φ)})  (13)where V_(SB) represents the source-body voltage of the turned-ontransistor;

V_(TO) represents the zero-V_(SB) value of threshold voltage;

γ represents a body-effect parameter; and

2φ represents the surface potential parameter.

In the embodiment, because the source and the body of the turned-ontransistor are coupled together, the source-body voltage V_(SB) is 0volt. Moreover, since the zero-V_(SB) value V_(TO), the body-effectparameter γ, and the surface potential parameter 2φ are constants, thetransistors N₀-N_(N) and NM₀-NM_(N) have the same threshold voltageV_(T). Therefore, if the transistors N₀-N_(N) and NM₀-NM_(N) have anidentical ratio W/L, the transistors N₀-N_(N) and NM₀-NM_(N) would havean identical turned-on transistor R_(ON). Generally, the output voltageV_(OUT) of the DAC 30 could be calculated according the equations(8)-(11).

Please refer to FIG. 4, which is a circuit diagram of a DAC 40 accordingto another embodiment of the present invention. The DAC 40 is similar tothe DAC 30 shown in FIG. 3. The major difference between the DAC 40 andthe DAC 30 is that the NMOSFETs N₀-N_(N) and NM₀-NM_(N) are replacedwith the p-channel metal-oxide-semiconductor field-effect transistors(PMOSFETs) P₀-P_(N) and PM₀-PM_(N). Each of the PMOSFETs P₀-P_(N) andPM₀-PM_(N) has a body and a source coupled to the body. The DAC 40 alsohas the negative feedback regulator 12, the reference resistor R_(REF),and a ladder circuit 42. The ladder circuit 42 has a plurality oftransistor-resistor units U₀-U_(N) connected in a string. In theembodiment, the resistance of each turned-on transistor R_(ON) could becalculated as follows:

$\begin{matrix}{R_{ON} = {\mu \times C_{OX} \times \frac{W}{L}\left( {V_{SG} - V_{T}} \right)}} & (14)\end{matrix}$where V_(SG) represents the source-gate voltage of the turned-ontransistor.

The threshold voltage V_(T) could be determined as follows:V _(T)=V _(TO)+γ(√{square root over (V _(BS)+2φ)}−√{square root over(2φ)})  (15)where V_(BS) represents the body-source voltage of the turned-ontransistor;

V_(TO) represents the zero-V_(BS) value of threshold voltage.

In the embodiment, because the source and the body of the turned-ontransistor are coupled together, the body-source voltage V_(BS) is 0volt. Moreover, since the zero-V_(BS) value V_(TO), the body-effectparameter γ, and the surface potential parameter 2φ are constants, thetransistors P₀-P_(N) and PM₀-PM_(N) have the same threshold voltageV_(T). Therefore, if the transistors P₀-P_(N) and PM₀-PM_(N) have anidentical ratio W/L, the transistors P₀-P_(N) and PM₀-PM_(N) would havean identical turned-on transistor R_(ON). Generally, the output voltageV_(OUT) of the DAC 40 could be calculated according the equations(8)-(11).

In view of the above, according to the present invention, each of thetransistor-resistor units of the DAC has a pair of transistors that areturned on/off by a pair of complementary control signals. Since the twotransistors of each transistor-resistor unit are positionedsymmetrically, an equivalent resistance would be determined preciselyaccording to received digital codes. Therefore, an output voltage of theDAC could be adjusted precisely based on the equivalent resistance.

It will be apparent to those skilled in the art that variousmodifications and variations can be made to the structure of the presentinvention without departing from the scope or spirit of the invention.In view of the foregoing, it is intended that the present inventioncover modifications and variations of this invention provided they fallwithin the scope of the following claims and their equivalents.

1. A digital to analog converter, comprising: an operational amplifierhaving an output terminal for outputting an output voltage; and a laddercircuit coupled to the output terminal, the ladder circuit having aplurality of transistor-resistor units connected in a string, each ofthe transistor-resistor units having a resistor, a first transistorcoupled to the resistor in series, and a second transistor coupled tothe resistor and the first transistor in parallel; wherein the firsttransistor is turned on while the second transistor is turned off, andthe first transistor is turned off while the second transistor is turnedon.
 2. The digital to analog converter as claimed in claim 1, wherein apair of complementary control signals is applied to the first transistorand the second transistor to turn on/off the first transistor and thesecond transistor.
 3. The digital to analog converter as claimed inclaim 1, wherein a turned-on resistance of the first transistor is equalto a turned-on resistance of the second transistor.
 4. The digital toanalog converter as claimed in claim 1, wherein the operationalamplifier further has a first input terminal coupled to a referencevoltage and a second input terminal coupled to one end of the laddercircuit.
 5. The digital to analog converter as claimed in claim 4further comprising a reference resistor coupled between the second inputterminal and a ground terminal.
 6. The digital to analog converter asclaimed in claim 1, wherein the first transistor and the secondtransistor are n-channel metal-oxide-semiconductor field-effecttransistors (NMOSFETs), each of the NMOSFETs has a body and a sourcecoupled to the body.
 7. The digital to analog converter as claimed inclaim 1, wherein the first transistor and the second transistor arep-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs),each of the PMOSFETs has a body and a source coupled to the body.
 8. Adigital to analog converting method for converting a plurality ofdigital codes into an output voltage, the method comprising: inputtingthe plurality of digital codes; generating a pair of complementarycontrol signals for each of the digital codes; applying the pairs ofcomplementary control signals to a series of pairs of transistors todetermine an equivalent resistance; and outputting the output voltagebased on the equivalent resistance; wherein each of the pairs oftransistors has a first transistor and a second transistor, the firsttransistor and the second transistor are connected in parallel, thefirst transistor is turned on while the second transistor is turned off,and the first transistor is turned off while the second transistor isturned on.
 9. The method as claimed in claim 8 further comprising:providing a reference voltage; and comparing the reference voltage witha terminal voltage of the series of pairs of transistors to refresh theoutput voltage.
 10. The method as claimed in claim 8, wherein each ofthe pairs of transistors further has a resistor, the resistor and thefirst transistor are connected in series.
 11. The method as claimed inclaim 8, wherein a turned-on resistance of the first transistor is equalto a turned-on resistance of the second transistor.
 12. The method asclaimed in claim 8, wherein the first transistor and the secondtransistor are n-channel metal-oxide-semiconductor field-effecttransistors (NMOSFETs), each of the NMOSFETs has a body and a sourcecoupled to the body.
 13. The method as claimed in claim 8, wherein thefirst transistor and the second transistor are p-channelmetal-oxide-semiconductor field-effect transistors (PMOSFETs), each ofthe PMOSFETs has a body and a source coupled to the body.
 14. A digitalto analog converter, comprising: an operational amplifier having anoutput terminal for outputting an output voltage and a negative inputterminal; and a ladder circuit coupled between the negative inputterminal and the output terminal, the ladder circuit having a pluralityof transistor-resistor units connected in a string, each of thetransistor-resistor units having a resistor, a first transistor coupledto the resistor in series, and a second transistor coupled to theresistor and the first transistor in parallel.